Towards automatic verification of ladder logic programs

Abstract : Control system programs are usually validated by testing prior to their deployment. Unfortunately, testing is not exhaustive and therefore it is possible that a program which passed all the required tests still contains errors. In this paper we apply techniques of automatic verification to a control program written in ladder logic. A model is constructed mechanically from the ladder logic program and subjected to automatic verification against requirements that include timing. This consists of an exhaustive search of the model of the program, thus eliminating the drawback of testing. We believe that automatic verification can substantially enhance current validation procedures for control programs.
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Bohumir Zoubek, Jean-Marc Roussel, Martha Kwiatkowska. Towards automatic verification of ladder logic programs. IMACS-IEEE "CESA'03" : "Computational Engineering in Systems Applications", Jul 2003, Lille, France. CD ROM paper S2-I-04-0169. ⟨hal-00354468⟩

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