OBTAINING TEMPORAL AND TIMED PROPERTIES OF LOGIC CONTROLLERS FROM FAULT TREE ANALYSIS

Abstract : One of the prerequisites for formal verification of logic controllers using model-checking is the formalization of properties to verify. The work presented in this paper proposes a method to elaborate the formal properties of a logic controller from a Fault Tree Analysis (FTA). The method developed here extends the traditional FTA with event ordering and timed information by introducing specific gates which model logic and physical time constraints. The behavior of these gates is then formalized in the form of state automata; formal properties are derived from the set of automata obtained at the end of FTA. A simple case study exemplifies the method.
Type de document :
Communication dans un congrès
Liste complète des métadonnées

https://hal.archives-ouvertes.fr/hal-00348083
Contributeur : Jean-Marc Faure <>
Soumis le : jeudi 18 décembre 2008 - 17:35:55
Dernière modification le : jeudi 9 février 2017 - 15:03:35
Document(s) archivé(s) le : mardi 8 juin 2010 - 16:33:56

Identifiants

  • HAL Id : hal-00348083, version 1

Collections

Citation

Israel Santiago Barragan, Matthias Roth, Jean-Marc Faure. OBTAINING TEMPORAL AND TIMED PROPERTIES OF LOGIC CONTROLLERS FROM FAULT TREE ANALYSIS. 12th IFAC Symposium on Information Control Problems in Manufacturing, INCOM 2006, May 2006, France. pp. 243-248. ⟨hal-00348083⟩

Partager

Métriques

Consultations de la notice

171

Téléchargements de fichiers

436