Test limit evaluation for an ADC Design-for-Test approach by using a CAT platform

Y. Lechuga (1) , Ahcène Bounceur (2) , R. Mozuelos (1) , M. Martinez (1) , S. Bracho (1) , Salvador Mir (2)

1 Electronics Technology, System and Automation Engineering Department
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper presents a Design-for-Test method for folded and interpolated analog-to-digital converters. The test approach samples relative voltage deviations among internal circuit nodes. A fault simulation is used to establish the fault detection threshold of the BIST by using a CAT platform.

Mots clés: circuit-simulation; built-in-test

Domaines: Micro et nanotechnologies/Microélectronique

Y. Lechuga, Ahcène Bounceur, R. Mozuelos, M. Martinez, S. Bracho, et al.. Test limit evaluation for an ADC Design-for-Test approach by using a CAT platform. 23rd International Conference on Design of Circuits and Integrated Systems (DCIS'08), Grenoble, France, November 12-14, Nov 2008, Grenoble, France. pp.session 1D2. ⟨hal-00347714⟩