FPGA Codesign Implementation of Vector Directional Filter

A. Boudabous (1) , Ahmed Ben Atitallah (1, 2) , Patrice Kadionik (2) , L. Khriji (3) , Nouri Masmoudi (1)

1 LETI - Laboratoire d'électronique et des technologies de l'Information [Sfax]
2 IMS - Laboratoire de l'intégration, du matériau au système
3 Dept. of Electrical and Computer Engineering

Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

Domaines: Micro et nanotechnologies/Microélectronique

A. Boudabous, Ahmed Ben Atitallah, Patrice Kadionik, L. Khriji, Nouri Masmoudi. FPGA Codesign Implementation of Vector Directional Filter. IPTTA: IEEE Workshop on Image Processing Theory, Tools and Application, Nov 2008, Sousse, Tunisia. pp 1-5, ⟨10.1109/IPTA.2008.4743773⟩. ⟨hal-00342695⟩