Dc and Low Frequency Noise analysis of hot-carrier induced degradation of low complexity 0.13 µm CMOS bipolar transistors, Microelectronics Reliability

Pascal Benoit (1) , Jérémy Raoult (2) , C. Delseny (2) , F. Pascal (2) , L. Snadny , J.C. Vildeuil , M. Marin , B. Martinet (3) , D. Cottin , O. Noblanc

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 CEM2 - Centre d'Electronique et de Micro-optoélectronique de Montpellier
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

The dc and the low frequency noise in Si bipolar junction transistors (BJTs) of a 0.13 μm CMOS technology are presented in this paper. In particular, the influence of a superficial base doping (SBD) layer is investigated in devices before and after hot-carrier stress induced degradation. A classical increase in the perimeter non-ideal (generation/recombination) base current is observed on stressed transistors. Prestress 1/f noise analysis shows that both surface and perimeter contribution are present. Their relative importance is dependent on presence or not of the SBD and of the geometry. After stress, a very significant increase in the 1/f noise level is measured. It is associated to the creation of a large number of traps at the emitter perimeter.

Domaines: Electronique

Pascal Benoit, Jérémy Raoult, C. Delseny, F. Pascal, L. Snadny, et al.. Dc and Low Frequency Noise analysis of hot-carrier induced degradation of low complexity 0.13 µm CMOS bipolar transistors, Microelectronics Reliability. Microelectronics Reliability, 2005, 45, pp.1800-1806. ⟨10.1016/j.microrel.2005.07.097⟩. ⟨hal-00329201⟩