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Top-down Design Methodology of a Multi-bit Continuous-Time Delta-Sigma Modulator

Abstract : Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a Continuous-Time Delta-Sigma Modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonideaties such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.
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Submitted on : Thursday, July 10, 2008 - 10:43:25 AM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM

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André Mariano, Dominique Dallet, Yann Deval, Jean-Baptiste Begueret. Top-down Design Methodology of a Multi-bit Continuous-Time Delta-Sigma Modulator. Analog Integrated Circuits and Signal Processing, Springer Verlag, 2009, 60 (1), pp.145-153. ⟨10.1007/s10470-008-9206-5⟩. ⟨hal-00294659⟩



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