Integrating abstract NoC models within MPSoC design

E. Moreno (1) , K. Popovici (2) , N. Calazans (1) , Ahmed Jerraya (2, 3)

1 PUC-RS - Pontifícia Universidade Católica do Rio Grande do Sul [Brasil] = Pontifical Catholic University of Rio Grande do Sul [Brazil] = Université catholique pontificale de Rio Grande do Sul [Brésil]
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
3 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

Current embedded applications are migrating from single processor¬based systems to intensive data communication requiring multiprocessing. The performance demanded by these applications requires the use of heterogeneous multiprocessing architectures in a single chip (MPSoCs) endowed with complex communication infrastructures, such as Networks on Chip or NoCs. NoC parameter choices, such as network dimensioning, topology, routing algorithm, and buffer sizing then become essential aspects for optimizing the implementation of such complex systems. This paper presents NoC models that allow evaluating communication architectures through the variation of parameters during MPSoC design. Applicability of the concepts is demonstrated through two heterogeneous MPSoC case studies: an MJPEG decoder and an H.264 encoder.

Mots clés: NoC-based-design; MPSOC

Domaines: Micro et nanotechnologies/Microélectronique

E. Moreno, K. Popovici, N. Calazans, Ahmed Jerraya. Integrating abstract NoC models within MPSoC design. Rapid System Prototyping Symposium (RSP'08), Jun 2008, Monterey, United States. pp.65-71, ⟨10.1109/RSP.2008.29⟩. ⟨hal-00293648⟩