Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Abstract : Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8–2 GHz bandwidth.
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https://hal.archives-ouvertes.fr/hal-00284746
Contributor : Equipe Conception de Circuits <>
Submitted on : Tuesday, June 3, 2008 - 4:04:59 PM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM

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André Mariano, Birama Goumballa, Dominique Dallet, Yann Deval, Jean-Baptiste Begueret. Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications. Analog Integrated Circuits and Signal Processing, Springer Verlag, 2008, 57 (79 - 87), pp.10.1007/s10470-008-9190-9. ⟨10.1007/s10470-008-9190-9⟩. ⟨hal-00284746⟩

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