D. Agrawal, J. R. Rao, P. Rohatgi, and K. Schramm, Templates as Master Keys, CHES, pp.15-29, 2005.
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T. Akishita, M. Katagi, Y. Miyato, A. Mizuno, and K. Shibutani, A Practical DPA Countermeasure with BDD Architecture, CARDIS, pp.206-217, 2008.
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C. Archambeau, E. Peeters, F. Standaert, and J. Quisquater, Template Attacks in Principal Subspaces, CHES, pp.1-14, 2006.
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V. Carlier, H. Chabanne, E. Dottax, and H. Pelletier, Generalizing square attack using side-channels of an AES implementation on an FPGA, International Conference on Field Programmable Logic and Applications, 2005., pp.433-437, 2005.
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S. Chari, J. R. Rao, and P. Rohatgi, Template Attacks, CHES, volume 2523, 2002.
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S. Chaudhuri, S. Guilley, P. Hoogvorst, J. Danger, T. Beyrouthy et al., Physical Design of FPGA Interconnect to Prevent Information Leakage, ARC (Applied Reconfigurable Computing), in LNCS, pp.87-98, 2008.
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J. A. Neil and . Sloane, The On-Line Encyclope- dia of Integer Sequences, published electronically at http://www.research.att.com/ ? njas/sequences/, Sequence A000372: Dedekind numbers: number of monotone Boolean functions of n variables or number of antichains of subsets of an n-set, 2009.

G. Rouvroy, F. Standaert, J. Quisquater, and J. Legat, Efficient uses of FPGAs for implementations of DES and its experimental linear cryptanalysis, IEEE Transactions on Computers, vol.52, issue.4, 2003.
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C. Giraud and H. Thiebeauld, A Survey on Fault Attacks, WCC/CARDIS, pp.159-176, 2004.
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S. Guilley, P. Hoogvorst, and R. Pacalet, A fast pipelined multi-mode DES architecture operating in IP representation, Integration, the VLSI Journal, vol.40, issue.4, pp.479-489, 2007.
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S. Guilley, P. Hoogvorst, R. Pacalet, J. Schmidt14, ]. E. De-mulder et al., Improving Side-Channel Attacks by Exploiting Substitution Boxes Properties Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems, BFCA, pp.1-255, 2007.

E. S?dd?ka-bernä-ors, B. Oswald, and . Preneel, Power-Analysis Attacks on an FPGA: First Experimental Results, CHES, pp.35-50, 2003.

T. Popp and S. Mangard, Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints, CHES, pp.172-186, 2005.
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T. Popp, T. Zefferer, and S. Mangard, Evaluation of the Masked Logic Style MDPL on a Prototype Chip, Proceedings of CHES'07, pp.81-94, 2007.
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J. Quisquater and D. Samyde, ElectroMagnetic Analysis (EMA): Measures and Counter-measures for Smart Cards, Smart Card Programming and Security (Esmart ), pp.200-210, 2001.
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F. Standaert, E. Peeters, F. Macé, and J. Quisquater, Updates on the Security of FPGAs Against Power Analysis Attacks, ARC, pp.335-346, 2006.
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F. Standaert, S. Bernä-ors, and B. Preneel, Power Analysis of an FPGA Implementation of Rijndael: Is Pipelining a DPA Countermeasure, CHES, pp.30-44

F. Standaert, G. Rouvroy, and J. Quisquater, FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks, 2006 International Conference on Field Programmable Logic and Applications, 2006.
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D. Suzuki and M. Saeki, Security Evaluation of DPA Countermeasures Using Dual-Rail Precharge Logic Style, Proceedings of CHES, pp.131-138, 2006.

K. Tiri and I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.246-251, 2004.
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K. Tiri and I. Verbauwhede, Secure Logic Synthesis, FPL, number 3203 in LNCS, pp.1052-1056, 2004.
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K. Tiri and I. Verbauwhede, Synthesis of Secure FPGA Implementations, International Workshop on Logic and Synthesis (IWLS), pp.224-231, 2004.

S. Trimberger, Trusted design in FPGAs, Proceedings of the 44th annual conference on Design automation, DAC '07, pp.5-8, 2007.
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P. Yu, Implementation of DPA-Resistant Circuit for FPGA. Master's thesis, Virginia Institute of Technology, 2007.