Design-for-Test of Asynchronous Networks-on-Chip

Xuan Tu Tran (1, 2) , Vincent Beroulle , Jean Durupt (1) , Chantal Robach (2) , François Bertrand (3)

1 DSYS - Département Systèmes
2 LCIS - Laboratoire de Conception et d'Intégration des Systèmes
3 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

Thanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system–on–chip (SoC) designers. Some asynchronous Networks–on–Chip (NoCs) architectures are proposed for the communication within SoCs, but lack of methodology and support formanufacture testing to ensure these communication architectures work correctly. In this paper, we present an innovative asynchronous DFT architecture that allows testing the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC–based SoCs. This asynchronous DFT architecture is implemented in Quasi Delay Insensitive (QDI) asynchronous circuits and uses an area of about 20 8 Kgates in an asynchronous NoC–based SoC of 4.5 Mgates without memories.

Mots clés: DfT; NoC; Asynchronous; FAUST

Domaines: Micro et nanotechnologies/Microélectronique

Xuan Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand. Design-for-Test of Asynchronous Networks-on-Chip. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, Czech Republic. pp. 163-167. ⟨hal-00218149⟩