Design of Class-E Power VCO in 65nm CMOS Technology: Application to RF Transmitter Architecture

Nathalie Deltimple 1 Yann Deval 1 Eric Kerherve 1 Didier Belot 2
1 IMS - Laboratoire de l'intégration, du matériau au système
2 ST-CROLLES - STMicroelectronics [Crolles]
Abstract : This paper investigates the feasibility of designing a RF TX architecture based on a Power VCO, operating at 1.95 GHz for UMTS/WCDMA standard. The Power VCO uses 2.5 V supply voltage and is designed using 65nm CMOS technology from ST Microelectronics. The Power VCO is made up of an oscillating Power Amplifier (PA). In order to fulfil UMTS/W CDMA requirements, especially on output power with regards to efficiency to save battery life, the used PA is a two-stage Class E PA. The output 1 dB compression point (CP1) is 22 dBm and Power Added Efficiency (PAE) @CP1 is 55.1%. This PA is then included in a loop to realize oscillation condition. The Power VCO oscillates @ 1.95GHz, achieves an output power of 23.3dBm with 60.3% PAE
Keywords : Power oscillator power amplifier RF CMOS integrated circuits
Document type :
Conference papers
Complete list of metadatas
https://hal.archives-ouvertes.fr/hal-00207360
Contributor : Nathalie Deltimple <>
Submitted on : Thursday, January 17, 2008 - 12:24:23 PM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM

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  • HAL Id : hal-00207360, version 1

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CNRS | IMS-BORDEAUX | IMS-BORDEAUX-FUSION

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Nathalie Deltimple, Yann Deval, Eric Kerherve, Didier Belot. Design of Class-E Power VCO in 65nm CMOS Technology: Application to RF Transmitter Architecture. 2008 IEEE International Symposium on Circuits and Systems (ISCAS2008), May 2008, Seattle, United States. pp. ⟨hal-00207360⟩

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