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A Complete Network-On-Chip Emulation Framework

Abstract : Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.
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Submitted on : Wednesday, October 24, 2007 - 11:22:12 AM
Last modification on : Thursday, February 25, 2021 - 9:46:04 AM
Long-term archiving on: : Monday, April 12, 2010 - 12:13:15 AM


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  • HAL Id : hal-00181642, version 1



N. Genko, D. Atienza, G. De Micheli, J. M. Mendias, R. Hermida, et al.. A Complete Network-On-Chip Emulation Framework. DATE'05, Mar 2005, Munich, Germany. pp.246-251. ⟨hal-00181642⟩



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