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Refinement Maps for Efficient Verification of Processor Models

Abstract : While most of the effort in improving verification times for pipeline machine verification has focused on faster decision procedures, we show that the refinement maps used also have a drastic impact on verification times. We introduce a new class of refinement maps for pipelined machine verification, and using the state-of-the-art verification tools UCLID and Siege we show that one can attain several orders of magnitude improvements in verification times over the standard flushing-based refinement maps, even enabling the verification of machines that are too complex to otherwise automatically verify.
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https://hal.archives-ouvertes.fr/hal-00181307
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Submitted on : Tuesday, October 23, 2007 - 2:37:40 PM
Last modification on : Wednesday, July 31, 2019 - 3:24:15 PM
Long-term archiving on: : Sunday, April 11, 2010 - 11:53:17 PM

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  • HAL Id : hal-00181307, version 1

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Panagiotis Manolios, Sudarshan K. Srinivasan. Refinement Maps for Efficient Verification of Processor Models. DATE'05, Mar 2005, Munich, Germany. pp.1304-1309. ⟨hal-00181307⟩

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