Refinement Maps for Efficient Verification of Processor Models

Panagiotis Manolios (1) , Sudarshan K. Srinivasan (2)

1 GATECH - College of Computing
2 ECE GeorgiaTech - School of Electrical and Computer Engineering - Georgia Insitute of Technology

While most of the effort in improving verification times for pipeline machine verification has focused on faster decision procedures, we show that the refinement maps used also have a drastic impact on verification times. We introduce a new class of refinement maps for pipelined machine verification, and using the state-of-the-art verification tools UCLID and Siege we show that one can attain several orders of magnitude improvements in verification times over the standard flushing-based refinement maps, even enabling the verification of machines that are too complex to otherwise automatically verify.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Panagiotis Manolios, Sudarshan K. Srinivasan. Refinement Maps for Efficient Verification of Processor Models. DATE'05, Mar 2005, Munich, Germany. pp.1304-1309. ⟨hal-00181307⟩