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IP Generation Targeting Multiple Bit-Width Standards

Bertrand Le Gal 1 Emmanuel Casseau 2
2 R2D2 - Reconfigurable and Retargetable Digital Devices
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, INRIA Rennes, ENSSAT - École Nationale Supérieure des Sciences Appliquées et de Technologie
Abstract : Multimedia applications such as video and image processing are computation intensive applications. For these applications the bit-width of data and operations is different all over the application. Generating optimized architectures is not an obvious task since it requires a deep bit-width analysis in order to properly size hardware resources. Furthermore implementing several application profiles onto the same chip makes it possible to avoid over-sized architectures or chip reconfiguration. In this paper we propose a design methodology based on high-level synthesis which takes into account multiple bit-width standards in order to generate area and power optimized architectures for embedded devices. First results demonstrate the interest of the approach.
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Contributor : Bertrand Le Gal <>
Submitted on : Wednesday, October 17, 2007 - 11:03:10 AM
Last modification on : Friday, November 20, 2020 - 11:44:08 AM


  • HAL Id : hal-00179954, version 1


Bertrand Le Gal, Emmanuel Casseau. IP Generation Targeting Multiple Bit-Width Standards. IEEE International Conference on Electronics, Circuits and Systems (ICECS'06), Dec 2006, Nice, France. pp.000. ⟨hal-00179954⟩



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