Return Path Assumption Validation for Inductance Modeling in Digital Design

Lauréline David (1) , Corinne Crégut (1) , Fabrice Huret (2) , Yves Quéré (2) , Frédéric Nyer (1)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 LEST - Laboratoire d'Electronique et Systèmes de Télécommunications

Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing relayout effective inductance estimations are suggested.

Mots clés: modeling; Digital circuit; inductance; interconnection; modeling.

Domaines: Micro et nanotechnologies/Microélectronique

Lauréline David, Corinne Crégut, Fabrice Huret, Yves Quéré, Frédéric Nyer. Return Path Assumption Validation for Inductance Modeling in Digital Design. IEEE Transactions on Advanced Packaging, 2007, 30 (2), pp.295-300. ⟨10.1109/TADVP.2007.896002⟩. ⟨hal-00176177⟩