Simplified Hardware Bit Correlator

Christophe Cunat (1) , Emmanuel Boutillon (1)

1 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel

This letter proposes a suboptimal implementation of a binary correlator suitable for detecting a known fixed pattern in a binary stream. The theoretical performances in terms of the probability of nondetection and the probability of false alarm are evaluated. These performances show that the degradations are negligible. Compared to a proprietary core provided by FPGA vendor, this implementation allows a 15 % look-up table reduction, a 30 % register reduction and up to a 30 % higher clock frequency in a FPGA.

Mots clés: Corrélateur binaire; FPGA

Domaines: Traitement du signal et de l'image [eess.SP]; Traitement du signal et de l'image [eess.SP]

Christophe Cunat, Emmanuel Boutillon. Simplified Hardware Bit Correlator. IEEE Communications Letters, 2007, 11 (6), pp.531 - 533. ⟨hal-00167354⟩