A DEVS-based Modeling Behavioral Fault Simulator for RT-Level Digital Circuits

Abstract : The domain of fault simulation for digital circuits described at the RT-level is currently under heavy researches. The goal of these researches is to define a fast and efficient methodology for the validation of test patterns very early in the design flow. We propose in this article a new approach for the modeling and the simulation of behavioral faults for digital circuits described in the VHDL language, using a discrete event approach. This methodology, based on the DEVS formalism, is implemented in a working prototype, and experimental results show the correctness of our approach and the efficiency of our behavioral fault simulator called BFS-DEVS. The fault model used to validate our results is essentially based on the stuck-at fault model since a good simple stuck-at faults coverage rate implies a good real faults coverage rate.
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Communication dans un congrès
SCS. SCS Summer Computer Simulation Conference (SCSC04), Jul 2004, San Jose, United States. SCS, pp.481-486, 2004
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Contributeur : Laurent Capocchi <>
Soumis le : jeudi 26 juillet 2007 - 11:34:28
Dernière modification le : lundi 21 mars 2016 - 17:31:37
Document(s) archivé(s) le : vendredi 9 avril 2010 - 00:04:52

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  • HAL Id : hal-00165460, version 1

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Laurent Capocchi, Fabrice Bernardi, Dominique Federici, Paul-Antoine Bisgambiglia. A DEVS-based Modeling Behavioral Fault Simulator for RT-Level Digital Circuits. SCS. SCS Summer Computer Simulation Conference (SCSC04), Jul 2004, San Jose, United States. SCS, pp.481-486, 2004. 〈hal-00165460〉

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