B. P. Zeigler, Theory of Modeling and Simulation, 1976.

M. Larsson, Behavioral and structural model based approaches to discrete diagnosis, 1999.

N. Giambiasi, J. Santucci, and A. Courbis, Test pattern generation for behavioral descriptions in VHDL, Proceedings of the Euro-VHDL Conference, 1991.
URL : https://hal.archives-ouvertes.fr/hal-00183321

J. Santucci, A. Courbis, and N. Giambiasi, Behavioral testing of digital circuits, Journal of Microelectronic System Integration, vol.1, issue.1
URL : https://hal.archives-ouvertes.fr/hal-00178330

E. Kofman, N. Giambiasi, and S. Junco, FDEVS: A general DEVS-based formalism for fault modeling and simulation, Proceedings of the European Simulation Symposium, 2000.

F. Corno, G. Cumani, M. S. Reorda, and G. Squillero, An RT-level fault model with high gate level correlation, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786), 2000.
DOI : 10.1109/HLDVT.2000.889551

G. Buonanno, L. F. Ferrandi, F. Fummi, and D. Sciuto, How an "evolving" fault model improves the behavioral test generation, Proceedings Great Lakes Symposium on VLSI, 1997.
DOI : 10.1109/GLSV.1997.580515

P. A. Thaker, V. D. Agrawal, and M. E. , Register-transfer level fault modeling and test evaluation techniques for VLSI circuits, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), 2000.
DOI : 10.1109/TEST.2000.894305

S. Gai, P. Montessoro, and F. Somenzi, The performance of the concurrent fault simulation algorithms in MOZART, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988., pp.692-697, 1988.
DOI : 10.1109/DAC.1988.14844

D. Machlin, D. Gross, S. Kadkade, and E. Ulrich, Switch level concurrent fault simulation based on a general purpose list trasversal mechanism, Proceedings of the International Test Conference, pp.574-581, 1988.

P. Montessoro and S. Gai, Creator, Proceedings of the 28th conference on ACM/IEEE design automation conference , DAC '91, pp.160-163, 1991.
DOI : 10.1145/127601.127653

A. Fin and F. Fummi, A VHDL error simulator for functional test generation, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), 2000.
DOI : 10.1109/DATE.2000.840301

G. S. Fulvio-corno and M. S. Reorda, RT-level fault simulation techniques based on simulation command scripts, Proceedings of the XV Conference on Design of Circuits and Integrated Systems, pp.825-830, 2000.

P. J. Ashenden, The designer guide to VHDL, 2001.

S. Seshu, On an Improved Diagnosis Program, IEEE Transactions on Electronic Computers, vol.14, issue.1, pp.76-79, 1965.
DOI : 10.1109/PGEC.1965.264063

D. Armstrong, A Deductive Method for Simulating Faults in Logic Circuits, IEEE Transactions on Computers, vol.21, issue.5, pp.464-471, 1972.
DOI : 10.1109/T-C.1972.223542

M. Abramovici, M. Breuer, and K. Kumar, Concurrent fault simulation and functional level modeling, Proceedings of the IEEE Design Automation Conference, pp.128-137, 1977.

S. Demba, E. Ulrich, K. Panetta, and D. Giramma, Experiences with concurrent fault simulation of diagnostic programs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.9, issue.6, pp.621-628, 1990.
DOI : 10.1109/43.55192

M. Kearney, DECSIM: A multi-level simulation system for digital design, Proceedings of the International Conference on Computer Design, pp.206-209, 1984.

S. Gai, F. Somenzi, and E. Ulrich, Advances in Concurrent Multilevel Simulation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.6, issue.6, pp.1006-10012, 1987.
DOI : 10.1109/TCAD.1987.1270341

C. Y. Lo, H. Nham, and A. Bose, Algorithms for an advanced fault simulation system in MOTIS, pp.232-240, 1987.

M. A. Breuer and A. C. Parker, Digital system simulation: Current status and futur trends, Proceedings of the IEEE Design Automation Conference, pp.269-275, 1981.
DOI : 10.1109/dac.1981.1585362

B. P. Zeigler, H. Praehofer, and T. G. Kim, Theory of Modeling and Simulation, 2000.

B. P. Zeigler, An introduction to set theory, 2003.

A. C. Chow and B. P. Zeigler, Abstract simulator for the parallel DEVS formalism, Fifth Annual Conference on AI, and Planning in High Autonomy Systems, 1994.
DOI : 10.1109/AIHAS.1994.390488

G. Wainer, S. Daicz, and A. Troccoli, Experiences in modeling and simulation of computer architectures in DEVS, Trans. Soc. Comput. Simul. Int, vol.18, issue.4, pp.179-202, 2001.

B. P. Zeigler and S. Vahie, Devs Formalism and Methodology: Unity of Conception/diversity of Application, Proceedings of 1993 Winter Simulation Conference, (WSC '93), pp.573-579, 1993.
DOI : 10.1109/WSC.1993.718101

B. P. Zeigler, DEVS theory of quantized systems, Tech. rep, 2004.

E. Gamma, R. Helm, R. Johnson, and J. Vlissides, Design Patterns, elements of reusable object-oriented software, 2002.

F. Corno, P. Prinetto, and M. S. Reorda, Testability analysis and ATPG on behavioral RT-level VHDL, Proceedings International Test Conference 1997, 1997.
DOI : 10.1109/TEST.1997.639688

O. Goloubeva, M. S. Reorda, and M. Violante, Behavioral-level fault models comparison: An experimental approach, Proceedings of the IEEE Computeraided Technologies in Applied Mathematics Conference, 2002.

P. Bisgambiglia, D. Federici, and J. Santucci, Fault modeling and simulation at behavioral level, Proceedings of LTAW01, pp.45-50, 2001.

L. Capocchi, F. Bernardi, D. Federici, and P. Bisgambiglia, Transformation of VHDL descriptions into DEVS models for fault modeling and simulation, Proceedings of the IEEE Systems, Man and Cybernetics Conference, pp.1205-1211, 2003.
URL : https://hal.archives-ouvertes.fr/hal-00165462

C. Paoli, M. Nivet, F. Bernardi, and L. Capocchi, Simulation-based validation of VHDL descriptions using constraints logic programming, Proceedings of the 5th IEEE Workshop on RTL and High Level Testing, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00440834