Simulation of assembly generated constraints during SMT processing and size optimisation of the capacitors by design of experiments

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https://hal.archives-ouvertes.fr/hal-00164908
Contributor : Yannick Deshayes <>
Submitted on : Tuesday, July 24, 2007 - 11:49:19 AM
Last modification on : Thursday, January 11, 2018 - 6:21:07 AM

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  • HAL Id : hal-00164908, version 1

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Y. Ousten, L. Bechou, N. Xiong. Simulation of assembly generated constraints during SMT processing and size optimisation of the capacitors by design of experiments. HYBRID CIRCUITS, 1993, pp. 26-32. ⟨hal-00164908⟩

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