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Article Dans Une Revue IEEE Journal of Solid-State Circuits Année : 2001

Analysis and Compact Modeling of a Vertical Grounded-Base NPN Bipolar Transistor used as ESD Protection in a Smart Power Technology

Marise Bafleur
Nicolas Nolhier
Jean-Marie Dorkel
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Quang Nguyen
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Nicolas Mauran
David Trémouilles

Résumé

A thorough analysis of the physical mechanisms involved in a Vertical Grounded-Base NPN bipolar transistor (VGBNPN) under ElectroStatic Discharge (ESD) stress is first carried out by using 2D-device simulation, Transmission Line Pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed.
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Dates et versions

hal-00143927 , version 1 (27-04-2007)

Identifiants

  • HAL Id : hal-00143927 , version 1

Citer

Géraldine Bertrand, Christelle Delage, Marise Bafleur, Nicolas Nolhier, Jean-Marie Dorkel, et al.. Analysis and Compact Modeling of a Vertical Grounded-Base NPN Bipolar Transistor used as ESD Protection in a Smart Power Technology. IEEE Journal of Solid-State Circuits, 2001, 36 (9), pp.1373-1381. ⟨hal-00143927⟩
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