Asynchronous on-line monitoring of PSL assertions

Katell Morin-Allory (1) , Laurent Fesquet (1) , D. Borrione (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

PSL is a standard formal language to specify logic and temporal properties in a declarative style, under the form of assertions. We defined a library of components, and an interconnection method to automatically synthesize hardware monitors that can be linked to a prototype of the design under verification, thus providing an efficient debugging platform. The existing tool produces on-line checkers that are clock synchronized with the monitored design. The on-going work aims at snooping the design with monitors built from asynchronous modules. The monitors are thus reliable in the case of truly asynchronous events, and become applicable to a wider range of verification tasks, notably the communications among globally asynchronous modules.

Mots clés: PSL; asynchronous circuits and systems

Domaines: Micro et nanotechnologies/Microélectronique

Katell Morin-Allory, Laurent Fesquet, D. Borrione. Asynchronous on-line monitoring of PSL assertions. Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), IEEE, 2006, Chania, Crète, Greece. pp.98 102, ⟨10.1109/RSP.2006.9⟩. ⟨hal-00130525⟩