Analysis and modeling of substrate impedance network in RF CMOS

Emmanuel Bouhana (1, 2) , Patrick Scheerer (2) , Samuel Boret (2) , Daniel Gloria (2) , Gilles Dambrine (1) , Michel Minondo (2) , Hervé Jaouen (2)

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
2 ST-CROLLES - STMicroelectronics [Crolles]

This paper presents a new approach for analyzing and modeling the substrate impedance network in RF CMOS. Thanks to preliminary and proper de-embedding of known parasitics, the substrate network is directly identified. Using this approach on MOS transistors from 130 down to 65 nm technologies allows to point out the respective implications of the isolation layer and the surrounding well plug on high-frequency characteristics. Their impacts are studied and a new model is proposed.

Mots clés: Semiconductor device modeling; Impedance; Intelligent networks; Radio frequency; Capacitance; Plugs; Isolation technology; Fingers; CMOS technology; MOSFET circuits

Domaines: Sciences de l'ingénieur [physics]

Emmanuel Bouhana, Patrick Scheerer, Samuel Boret, Daniel Gloria, Gilles Dambrine, et al.. Analysis and modeling of substrate impedance network in RF CMOS. IEEE International Conference on Microelectronic Test Structures, Mar 2006, Austin, TX, United States. pp.65-70, ⟨10.1109/ICMTS.2006.1614277⟩. ⟨hal-00126801⟩