Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping

J. Quartana (1) , Laurent Fesquet (1) , Marc Renaudin (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper presents an innovating methodology for fast and easy design of Asynchronous Network-on-Chips (ANoCs) dedicated to GALS systems. A topology-independent building-block approach permits to design modular, scalable and reliable ANoCs with low-power and low-complexity requirements. A crossbar generator is added to the existing design flow for fast system architecture exploration. A multi-clock FPGA allows a fast prototyping of a complex ANoC-centric GALS system. It includes synchronous standard IP cores and asynchronous modules connected through an asynchronous 5x5 crossbar. First results about communication costs/performances across the Asynchronous NoC are reported.

Mots clés: asynchronous; GALS systems

Domaines: Micro et nanotechnologies/Microélectronique

J. Quartana, Laurent Fesquet, Marc Renaudin. Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. 15th IFIP International Conference on Very Large Scale Integration Systems (VLSI-SoC'05), 2005, Perth, Australia. pp.397-402. ⟨hal-00104233⟩