Memory Aware High-Level Synthesis for Embedded Systems

Gwenolé Corre (1) , Eric Senn (2) , Nathalie Julien (2) , Eric Martin (2)

1 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel
2 Lab-STICC_UBS_CACS_MOCS

We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory mapping as a set of constraints used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Finally, we show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

Mots clés: HLS tool; memory constraint; memory accesses

Domaines: Architectures Matérielles [cs.AR]

Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin. Memory Aware High-Level Synthesis for Embedded Systems. IADIS conference on Applied Computing, 2004, Lisbonne, Portugal. pp.499-506. ⟨hal-00077375⟩