Modeling and design of asynchronous priority arbiters for on-chip

Jean-Baptiste Rigaud (1) , J. Quartana (1) , Laurent Fesquet (1) , Marc Renaudin (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper adresses the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studies in the perspective of making easier and more practical the design of future GALS or GALA SoCs. The paper focuses on high-level modeling and delay-insensitive implementations of fixed and dynamic priority arbiter. Pre-layout simulations show that arbiters which are able to process several hundreds mega requests per second can be designed using the 0.18 µm CMOS process of STMicroelectronics.

Mots clés: asynchronous systems; priority arbiters; high-level modeling; CHP language; QDI circuits

Domaines: Micro et nanotechnologies/Microélectronique

Jean-Baptiste Rigaud, J. Quartana, Laurent Fesquet, Marc Renaudin. Modeling and design of asynchronous priority arbiters for on-chip. SOC Design Methodologies Series: IFIP International Federation for Information Processing, Kluwer Academic Publishers, 496 p., pp.313-324, 2002, Vol. 90;. ⟨hal-00016196⟩