Taking advantage of ASICs to improve dependability with very low overheads [PLC]

T. Michel (1) , Régis Leveugle (1, 2) , G. Saucier (1) , R. Doucet (3) , P. Chapier (3)

1 CSI - CSI, INPG, Grenoble
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
3 Télémécanique Electrique - Sophia Antipolis

On-line test mechanisms have been designed for the CPU of a programmable logic controller. Specific devices integrated in an ASIC processor perform control flow checking during both application and system program executions. A prototype has been implemented, demonstrating the very low overhead of the approach. Results of fault injections have then proved the dependability increase at system level.

Mots clés: ASIC-processor; system-level-dependability-improvement; online-test-mechanisms; CPU-architecture; programmable-logic-controller; control-flow-checking; very-low-overhead; fault-injections; fault-detection; signature-monitoring-schemes; error-detection-mechanisms

Domaines: Micro et nanotechnologies/Microélectronique

T. Michel, Régis Leveugle, G. Saucier, R. Doucet, P. Chapier. Taking advantage of ASICs to improve dependability with very low overheads [PLC]. Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6, 1994, Paris, France. pp.14-18, ⟨10.1109/EDTC.1994.326905⟩. ⟨hal-00015209⟩