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PREVAIL: a proof environment for VHDL descriptions

Abstract : The authors describe a formal verification environment for proving the equivalence of two VHDL architectures of the same design entity, provided the designer conforms to some restrictions in the description style. For simple bit-level combinational descriptions, the environment calls upon a tautology checker. For parameterized repetitive structures, and designs described at a more abstract level, the descriptions are translated into recursive functions, according to pre-defined templates, and a theorem is generated in a form acceptable by the Boyer-Moore theorem prover. For well identified classes of circuits, the proof is fully automatic.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, November 22, 2005 - 3:06:33 PM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM


  • HAL Id : hal-00014249, version 1



D. Borrione, Laurence Pierre, A. Salem. PREVAIL: a proof environment for VHDL descriptions. Correct-Hardware-Design-Methodologies.-Proceedings-of-the-Advanced-Research-Workshop., 1992, Turin, Italy. pp.163-86. ⟨hal-00014249⟩



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