A process algebra interpretation of a verification oriented overlanguage of VHDL

C. Bayol (1) , B. Soulas (1) , F. Corno (2) , P. Prinetto (2) , D. Borrione (3)

1 EDF R&D - EDF R&D
2 Polito - Politecnico di Torino = Polytechnic of Turin
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

The VOVHDL language was defined as a verification oriented VHDL-based language in order to obtain a VHDL simulable specification at system level and to be able to verify this specification in a process algebra approach. The paper presents a formal semantic model for VOVHDL in terms of parallel composition of labelled transition systems, and its implementation with the EVAL CCS-based verification tool.

Mots clés: process-algebra-interpretation; verification-oriented-overlanguage; VHDL-; VOVHDL-language; verification-oriented-VHDL-based-language; VHDL-simulable-specification; system-level; formal-semantic-model; parallel-composition; labelled-transition-systems; EVAL-CCS-based-verification-tool

Domaines: Micro et nanotechnologies/Microélectronique

C. Bayol, B. Soulas, F. Corno, P. Prinetto, D. Borrione. A process algebra interpretation of a verification oriented overlanguage of VHDL. Proceedings-EURO-DAC-'94-with-EURO-VHDL-'94-IEEE-Cat.-No.94CH35704., 1994, Grenoble, France. pp.506-11. ⟨hal-00014238⟩