Denotational semantics of a synchronous VHDL subset

D. Borrione (1) , A. Salem (2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 ASU - Ain Shams University

A denotational definition for a single clock synchronous subset of VHDL is proposed. The different domains for variables and signals, the elaboration of static environments, and the formulation of a simulation algorithm for the sub-language characterize this definition, and distinguish it from more traditional denotational semantics of programming languages.

Mots clés: denotational-semantics; synchronous-VHDL-subset; single-clock-synchronous-subset; variables-domain; signals-domain; static-environment-elaboration; simulation-algorithm; sublanguage-; VHDL-elaboration; VHDL-simulation-cycle

Domaines: Micro et nanotechnologies/Microélectronique

D. Borrione, A. Salem. Denotational semantics of a synchronous VHDL subset. Formal Methods in System Design, 1995, Aug. ; 7(1-2), pp.53-71. ⟨hal-00014235⟩