Shorts in self-checking circuits

M. Nicolaidis (1, 2)

1 IROC TECHNOLOGIES - iROc Technologies
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

A detailed analysis of the consequences of shorts in self-checking NMOS and CMOS circuits are given. Many of these consequences are different from those of other fault models that do not include shorts. The coverage of the different types of shorts by existing techniques is examined. It is shown that the existing techniques are capable of handling some short types, and supplementary techniques are proposed when the existing techniques break down.

Mots clés: logic-testing; self-checking-circuits; shorts-; NMOS-; CMOS-; fault-models

Domaines: Micro et nanotechnologies/Microélectronique

M. Nicolaidis. Shorts in self-checking circuits. International-Test-Conference-1987-Proceedings:-Integration-of-Test-with-Design-and-Manufacturing-Cat.-No.87CH2347-2, 1987, Washington, DC, France. pp.408-17. ⟨hal-00014077⟩