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Communication Dans Un Congrès Année : 1995

Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

Résumé

This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction.
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Dates et versions

hal-00013893 , version 1 (15-11-2005)

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T. Calin, F. Hernan Vargas, M. Nicolaidis. Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments. Proceedings.-International-Test-Conference-IEEE-Cat.-No.95CH35858, 1995, Washington, DC, United States. pp.45-53, ⟨10.1109/TEST.1995.529816⟩. ⟨hal-00013893⟩

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