Fault-secure parity prediction Booth multipliers

M. Nicolaidis (1, 2) , R.-O. Duarte (2)

1 IROC TECHNOLOGIES - iROc Technologies
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding.

Mots clés: Booth-multipliers; parity-prediction; fault-secure-design; operand-recoding; arithmetic-operators

Domaines: Micro et nanotechnologies/Microélectronique

M. Nicolaidis, R.-O. Duarte. Fault-secure parity prediction Booth multipliers. IEEE Design & Test, 1999, July-Sept. ; 16(3), pp.90-101. ⟨10.1109/54.785842⟩. ⟨hal-00013808⟩