New methods for evaluating the impact of single event transients in VDSM ICs

D. Alexandrescu (1) , Lorena Anghel (1) , M. Nicolaidis (1, 2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 IROC TECHNOLOGIES - iROc Technologies

This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.

Mots clés: single-event-transient; VDSM-ICs; very-deep-submicron-ICs; SET-fault-simulation-technique; probability-; combinational-logic; storage-cell

Domaines: Micro et nanotechnologies/Microélectronique

D. Alexandrescu, Lorena Anghel, M. Nicolaidis. New methods for evaluating the impact of single event transients in VDSM ICs. Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002, 2002, Vancouver, BC, Canada. pp.99-107, ⟨10.1109/DFTVS.2002.1173506⟩. ⟨hal-00013736⟩