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Communication Dans Un Congrès Année : 2005

An efficient BICS design for SEUs detection and correction in semiconductor memories

Résumé

We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.
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Dates et versions

hal-00013724 , version 1 (10-11-2005)

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Citer

B. Gill, M. Nicolaidis, F. Wolff, C. Papachristou, S. Garverick. An efficient BICS design for SEUs detection and correction in semiconductor memories. Proceedings.-Design,-Automation-and-Test-in-Europe, 2005, Munich, Germany. pp.592-7 Vol. 1, ⟨10.1109/DATE.2005.54⟩. ⟨hal-00013724⟩

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