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ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor

Abstract : The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructions in-order and completes their execution out-of-order, and it can be customized both at the hardware and software levels to fit specific application requirements. Its architecture extensively uses an overlapping pipelined execution scheme involving desynchronized units. The design flow and circuit style are an original application of A. Martin's method. The expected performance is 200 peak MIPS, 0.5 Watt using a 0.25 mu m technology.
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https://hal.archives-ouvertes.fr/hal-00011217
Contributor : Lucie Torella Connect in order to contact the contributor
Submitted on : Thursday, October 13, 2005 - 3:12:21 PM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM

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Marc Renaudin, Pascal Vivet, F. Robin. ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor. Proceedings.-Fourth-International-Symposium-on-Advanced-Research-in-Asynchronous-Circuits-and-Systems-Cat.-No.98EX138, 1998, San Deigo, CA,, United States. pp.22-31, ⟨10.1109/ASYNC.1998.666491⟩. ⟨hal-00011217⟩

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