. Altera-2008a, Floating Point Exponent (ALTFP EXP) Megafunction User Guide, Altera

. Altera-2008b, Floating Point Natural Logarithm (ALTFP LOG) Megafunction User Guide, Altera

S. Banescu, F. De-dinechin, B. Pasca, and R. Tudoran, Multipliers for floating-point double precision and beyond on FPGAs, ACM SIGARCH Computer Architecture News, vol.38, issue.4, pp.73-79, 2010.
DOI : 10.1145/1926367.1926380
URL : https://hal.archives-ouvertes.fr/ensl-00475781

P. Belanovi´cbelanovi´c and M. Leeser, A library of parameterized floating-point modules and their use, Field Programmable Logic and Applications, pp.657-666, 2002.

M. R. Bodnar, J. R. Humphrey, P. F. Curt, J. P. Durbano, and D. W. Prather, Floating-Point Accumulation Circuit for Matrix Applications, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp.303-304, 2006.
DOI : 10.1109/FCCM.2006.41

F. De-dinechin, A flexible floating-point logarithm for reconfigurable computers, 2010.
URL : https://hal.archives-ouvertes.fr/ensl-00506122

F. De-dinechin, M. Joldes, and B. Pasca, Automatic generation of polynomial-based hardware architectures for function evaluation, ASAP 2010, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, 2010.
DOI : 10.1109/ASAP.2010.5540952
URL : https://hal.archives-ouvertes.fr/ensl-00470506

F. De-dinechin, C. Q. Lauter, and J. Muller, Fast and correctly rounded logarithms in double-precision, RAIRO - Theoretical Informatics and Applications, vol.41, issue.1, pp.85-102, 2007.
DOI : 10.1051/ita:2007003
URL : https://hal.archives-ouvertes.fr/ensl-00000007

F. De-dinechin and B. Pasca, Floating-point exponential functions for DSP-enabled FPGAs, 2010 International Conference on Field-Programmable Technology, pp.110-117, 2010.
DOI : 10.1109/FPT.2010.5681764
URL : https://hal.archives-ouvertes.fr/ensl-00506125

F. De-dinechin and B. Pasca, Designing Custom Arithmetic Data Paths with FloPoCo, IEEE Design & Test of Computers, vol.28, issue.4, 2011.
DOI : 10.1109/MDT.2011.44
URL : https://hal.archives-ouvertes.fr/ensl-00646282

F. De-dinechin, B. Pasca, . Cret¸, O. Cret¸, and R. Tudoran, An FPGA-specific approach to floatingpoint accumulation and sum-of-products, Field-Programmable Technologies. IEEE, pp.33-40, 2008.
URL : https://hal.archives-ouvertes.fr/ensl-00268348

J. Detrey and F. De-dinechin, Table-based polynomials for fast hardware function evaluation, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), pp.328-333, 2005.
DOI : 10.1109/ASAP.2005.61

J. Detrey and F. De-dinechin, Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems, Special Issue on FPGA-based Reconfigurable Computing 31, pp.537-545, 2007.
URL : https://hal.archives-ouvertes.fr/ensl-00542213

J. Detrey, F. De-dinechin, and X. Pujol, Return of the hardware floating-point elementary function, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp.161-168, 2007.
DOI : 10.1109/ARITH.2007.29
URL : https://hal.archives-ouvertes.fr/ensl-00117386

C. C. Doss and R. L. Riley, FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp.229-238, 2004.
DOI : 10.1109/FCCM.2004.38

P. Echeverrí-a-aramendi, Hardware acceleration of Monte Carlo-based simulations, 2011.

P. Echeverría and M. López-vallejo, An FPGA implementation of the powering function with single precision floating point arithmetic, 8th Conference on Real Numbers and Computers, pp.17-26, 2008.

P. Echeverría and M. López-vallejo, Customizing floating-point units for FPGAs: Area-performance-standard trade-offs, Microprocessors and Microsystems, vol.35, issue.6, pp.535-546, 2011.
DOI : 10.1016/j.micpro.2011.04.004

M. Ercegovac, Radix-16 Evaluation of Certain Elementary Functions, IEEE Transactions on Computers, vol.22, issue.6, pp.561-566, 1973.
DOI : 10.1109/TC.1973.5009107

D. Harris, An exponentiation unit for an OpenGL lighting engine, IEEE Transactions on Computers, vol.53, issue.3, pp.251-258, 2004.
DOI : 10.1109/TC.2004.1261833

I. Kuon and J. Rose, Measuring the Gap Between FPGAs and ASICs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.2, pp.203-215, 2007.
DOI : 10.1109/TCAD.2006.884574

C. Lauter and V. Lefèvre, An Efficient Rounding Boundary Test for {\rm pow}(x, y) in Double Precision, IEEE Transactions on Computers, vol.58, issue.2, pp.197-207, 2009.
DOI : 10.1109/TC.2008.202

L. Louca, T. Cook, J. , and W. , Implementation of IEEE single precision floating point addition and multiplication on FPGAs, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96, pp.107-116, 1996.
DOI : 10.1109/FPGA.1996.564761

Z. Luo and M. Martonosi, Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques, IEEE Transactions on Computers, vol.49, issue.3, pp.208-218, 2000.
DOI : 10.1109/12.841125

P. Markstein, IA-64 and Elementary Functions: Speed and Precision. Hewlett-Packard Professional Books, 2000.

J. Muller, Elementary Functions, Algorithms and Implementation, 2006.
URL : https://hal.archives-ouvertes.fr/ensl-00000008

J. A. Piñeiro, M. D. Ercegovac, and J. D. Bruguera, Algorithm and architecture for logarithm, exponential, and powering computation, IEEE Transactions on Computers, vol.53, issue.9, pp.1085-1096, 2004.
DOI : 10.1109/TC.2004.53

R. Pottathuparambil and R. Sass, A parallel/vectorized double-precision exponential core to accelerate computational science applications, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '09, pp.285-285, 2009.
DOI : 10.1145/1508128.1508198

R. Rebonato, Modern pricing of interest-rate derivatives: The LIBOR market model and beyond, 2002.
DOI : 10.1515/9781400829323

R. Scrofano, M. Gokhale, F. Trouw, and V. Prasanna, Accelerating Molecular Dynamics Simulations with Reconfigurable Computers, IEEE Transactions on Parallel and Distributed Systems, vol.19, issue.6, pp.764-778, 2008.
DOI : 10.1109/TPDS.2007.70777

N. Shirazi, A. Walters, and P. Athanas, Quantitative analysis of floating point arithmetic on FPGA based custom computing machines, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, pp.155-162, 1995.
DOI : 10.1109/FPGA.1995.477421

P. Tang, Table-driven implementation of the exponential function in IEEE floating-point arithmetic, ACM Transactions on Mathematical Software, vol.15, issue.2, pp.144-157, 1989.
DOI : 10.1145/63522.214389

K. Underwood, FPGAs vs. CPUs, Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays , FPGA '04, pp.171-180, 2004.
DOI : 10.1145/968280.968305

A. Vázquez and E. Antelo, Implementation of the exponential function in a floating-point unit, Journal of VLSI Signal Processing, vol.33, pp.1-2, 2003.

X. Wang, S. Braganza, and M. Leeser, Advanced components in the variable precision floatingpoint library, pp.249-258, 2006.

M. Wielgosz, E. Jamro, and K. Wiatr, Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function, ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications, pp.306-311, 2009.
DOI : 10.1007/978-3-540-78610-8_28

K. E. Wires, M. J. Schulte, and D. Mccarley, FPGA Resource Reduction Through Truncated Multiplication, Field-Programmable Logic and Applications, pp.574-583, 2001.
DOI : 10.1007/3-540-44687-7_59

N. Woods and T. Vancourt, FPGA acceleration of quasi-Monte Carlo in finance. Field Programmable Logic and Applications, pp.335-340, 2008.

C. Wrathall and T. C. Chen, Convergence guarantee and improvements for a fast hardware exponential and logarithm evaluation scheme, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH), pp.175-182, 1978.
DOI : 10.1109/ARITH.1978.6155762

L. Zhuo and V. Prasanna, High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware, IEEE Transactions on Computers, vol.57, issue.8, pp.1057-1071, 2008.
DOI : 10.1109/TC.2008.55

A. Ziv, Fast evaluation of elementary mathematical functions with correctly rounded last bit, ACM Transactions on Mathematical Software, vol.17, issue.3, pp.410-423, 1991.
DOI : 10.1145/114697.116813