Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter

Loic Zussa (1) , Jean-Max Dutertre (1) , Jessy Clediere (2) , Bruno Robisson (3)

1 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 Laboratoire Systèmes et Architectures Sécurisés (LSAS)

Power supply underpowering and negative power supply glitches are commonly used for the purpose of injecting faults into secure circuits. The related fault injection mechanism has been extensively studied: it is based on setup time violations. Positive power supply glitches are also used to inject faults. However, an increase of the supply voltage is not consistent with a mechanism based on setup time violation. Besides, no research work has yet identified the corresponding mechanism. In this work, we report the use of an embedded delay-meter to monitor the core voltage of a programmable device exposed to power supply glitches. It permitted us to gain a further insight into the mechanism associated with power glitches and also to identify the injection mechanism of positive power supply glitches.

Mots clés: Fault Injection; power supply glitch; on chip voltmeter; FPGA; field-programmable gate array

Domaines: Sciences de l'ingénieur [physics]; Micro et nanotechnologies/Microélectronique

Loic Zussa, Jean-Max Dutertre, Jessy Clediere, Bruno Robisson. Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter. IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST), May 2014, Arlington, France. ⟨10.1109/HST.2014.6855583⟩. ⟨emse-01099010⟩