An Approach Combining Simulation and Verification for SysML using SystemC and Uppaal

Abstract : Ensuring the correction of heterogeneous and complex systems is an essential stage in the process of engineering systems. In this paper we propose a methodology to verify and validate complex systems specified with SysML language using a combination of the two techniques of simulation and verification. We translate SysML specifications into SystemC models to validate the designed systems by simulation, then we propose to verify the derived SystemC models by using the Uppaal model checker. A case study is presented to demonstrate the effectiveness of our approach.