Since their introduction, CMOS devices have shrunk exponentially in size following Moore’s Law which predicts a doubling of transistors per integrated circuit every 18 months. However, the ability to increase CMOS performance by decreasing the transistor size is reaching some limits. In this perspective, there is a need to introduce new materials and add new functionalities to nanoelectronics integrated circuits.
In this perspective, our research activities go from the materials to the devices, at the nanometer scale. To reach our objectives, both top-down and bottom-up approaches are combined. We study the elaboration of dielectric, metallic and semiconducting nanomaterials (0D, 1D, 2D), nanostructures selfassembling mechanisms, physical properties of nanomaterials and their integration in devices.
Equilibrium between advanced and applied research topics is maintained through collaborations with industrial partners, namely STMicroelectronics and an equipment supplier (ALTATECH). On the other hand, we have developed a strong collaboration with academic French partners via national project, european partners via the SiNano and NanoSil Excellence European Networks and international partners like Santa Barbara University and Sherbrooke University.
Currently, our main research topics are...
- Memories operating at high temperature (charge straps, PCRAM, ReRAM)
- 3D integration based on nanowires growth (Si, Ge NWs VLS growth, 3D integration, new fonctionnalities)
- Biological and colloidal nanodevices