Using Model Checking to Identify Timing Interferences on Multicore Processors

Viet Anh Nguyen (1) , Eric Jenn (1) , Wendelin Serwe (2) , Frederic Lang (2) , Radu Mateescu (2)

1 IRT Saint Exupéry - Institut de Recherche Technologique
2 CONVECS - Construction of verified concurrent systems

Mots clés: AURIX TriCore; Index Terms Multicore; Timing interference; Model checking; CADP

Domaines: Génie logiciel [cs.SE]; Calcul parallèle, distribué et partagé [cs.DC]

Viet Anh Nguyen, Eric Jenn, Wendelin Serwe, Frederic Lang, Radu Mateescu. Using Model Checking to Identify Timing Interferences on Multicore Processors. ERTS 2020 - 10th European Congress on Embedded Real Time Software and Systems, Jan 2020, Toulouse, France. pp.1-10. ⟨hal-02462085⟩