.:. Browse > By authors > Nassar .:.

7 documents ordered by : Date Title first author name document type Submit date

RSM: a Small and Fast Countermeasure for AES, Secure against 1st and 2nd-order Zero-Offset SCAs Nassar M. Antoine Alexandre, Souissi Y., Guilley S., Danger J.-L. Dans Proceedings of DATE - Design Automation and Test in Europe, Allemagne (2012) [hal-00666337 - version 1]

Vade Mecum on Side-Channels Attacks and Countermeasures for the Designer and the Evaluator Guilley S., Meynard O., Nassar M., Duc G., Hoogvorst P., Maghrebi H., Elaabid A., Bhasin S., Souissi Y., Debande N. et al Dans DTIS - Design & Technology of Integrated Systems, Grèce (2011) [hal-00579020 - version 2]

Vade Mecum on Side-Channels Attacks and Countermeasures for the Designer and the Evaluator Guilley S., Meynard O., Nassar M., Duc G., Hoogvorst P., Maghrebi H., Elaabid A., Bhasin S., Souissi Y., Debande N. et al Dans DTIS - Design & Technology of Integrated Systems, Grèce (2011) [hal-00579020 - version 1]

Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation-Level Attacks on Hardware Cryptoprocessors Danger J.-L., Guilley S., Bhasin S., Nassar M., Sauvage L. [hal-00431261 - version 1] (11/11/2009)

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow Bhasin S., Danger J.-L., Flament F., Graba T., Guilley S., Mathieu Y., Nassar M., Sauvage L., Selmane N. Dans International Conference on ReConFigurable Computing and FPGAs - ReConFig, Mexique (2009) [hal-00411843 - version 3]

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow Bhasin S., Danger J.-L., Flament F., Graba T., Guilley S., Mathieu Y., Nassar M., Sauvage L., Selmane N. Dans International Conference on ReConFigurable Computing and FPGAs - ReConFig, Mexique (2009) [hal-00411843 - version 2]

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow Bhasin S., Danger J.-L., Flament F., Graba T., Guilley S., Mathieu Y., Nassar M., Sauvage L., Selmane N. [hal-00411843 - version 1] (30/08/2009)

Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints. Sauvage L., Guilley S., Danger J.-L., Mathieu Y., Nassar M. Dans Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09. - Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., France (2009) [hal-00325417 - version 3]

Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor. Sauvage L., Guilley S., Danger J.-L., Mathieu Y., Nassar M. [hal-00339858 - version 1] (2008-11-19)

Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints. Sauvage L., Guilley S., Danger J.-L., Mathieu Y., Nassar M. [hal-00325417 - version 2] (18/11/2008)