| Type de publication : |
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Articles dans des revues avec comité de lecture |
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| Domaine : |
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Informatique/Autre
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| Titre : |
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An Efficient Memory Operations Optimization Technique for Vector Loops on Itanium 2 Processors |
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| Auteur(s) : |
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Jalby William 1, Christophe Lemuet 1, Sid-Ahmed-Ali TOUATI 1 |
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| Laboratoire : |
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| Résumé : |
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To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. In this paper, we study the impact of these cache systems on memory instructions scheduling. We demonstrate that, if no care is taken at compile time, the non-precise memory disambiguation mechanism and the banking structure cause severe performance loss, even for very simple regular codes. We also show that grouping the memory operations in a pseudo-vectorized way enables the compiler to generate more effective code for the Itanium 2 processor. The impact of this code optimization technique on register pressure is analyzed for various vectorization schemes. |
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Langue du texte
intégral : |
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Anglais |
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| Journal : |
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| Concurrency and Computation: Practice and Experience |
| Publisher |
Wiley-Blackwell |
| ISSN |
1532-0626 (eISSN : 1532-0634) |
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| Audience : |
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internationale |
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| Date de publication : |
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09/2006 |
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| Volume : |
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18 |
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| Numéro : |
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11 |
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| Page, identifiant, ... : |
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1485-1508 |
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| Mots Clés : |
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performance measurement – cache optimization – memory access optimization – bank conflicts – memory address disambiguation – instruction level parallelism |
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