| Type de publication : |
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Communications avec actes |
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| Domaine : |
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Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique
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| Titre : |
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IP Generation Targeting Multiple Bit-Width Standards |
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| Auteur(s) : |
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Bertrand Le Gal ( ) 1, Emmanuel Casseau 2 |
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| Laboratoire : |
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| 1 : |
Laboratoire de l'intégration, du matériau au système (IMS) |
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CNRS : UMR5218 – Université Sciences et Technologies - Bordeaux I – Institut Polytechnique de Bordeaux |
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33405 TALENCE CEDEX |
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France |
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| 2 : |
R2D2 (INRIA - IRISA) |
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CNRS : UMR6074 – INRIA – Institut National des Sciences Appliquées (INSA) - Rennes – Ecole Nationale Supérieure des Sciences Appliquées et de Technologie (ENSSAT) – Université de Rennes 1 |
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France |
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| Résumé : |
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Multimedia applications such as video and image processing are computation intensive applications. For these applications the bit-width of data and operations is different all over the application. Generating optimized architectures is not an obvious task since it requires a deep bit-width analysis in order to properly size hardware resources. Furthermore implementing several application profiles onto the same chip makes it possible to avoid over-sized architectures or chip reconfiguration. In this paper we propose a design methodology based on high-level synthesis which takes into account multiple bit-width standards in order to generate area and power optimized architectures for embedded devices. First results demonstrate the interest of the approach. |
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Langue du texte
intégral : |
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Anglais |
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| Titre de l'ouvrage : |
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the Proceeding of 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS'06) |
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| Audience : |
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internationale |
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| Date de publication : |
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12/2006 |
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| Page, identifiant, ... : |
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000 |
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| Titre de la conférence : |
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IEEE International Conference on Electronics, Circuits and Systems (ICECS'06) |
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| Date de la conférence : |
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10/12/2006 |
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| Ville : |
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Nice |
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| Pays : |
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France |
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