IP Generation Targeting Multiple Bit-Width Standards

Bertrand Le Gal; Emmanuel Casseau

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IEEE International Conference on Electronics, Circuits and Systems (ICECS'06), Nice : France (2006)

IP Generation Targeting Multiple Bit-Width Standards

Bertrand Le Gal ¹, Emmanuel Casseau ²

(12/2006)

Multimedia applications such as video and image processing are computation intensive applications. For these applications the bit-width of data and operations is different all over the application. Generating optimized architectures is not an obvious task since it requires a deep bit-width analysis in order to properly size hardware resources. Furthermore implementing several application profiles onto the same chip makes it possible to avoid over-sized architectures or chip reconfiguration. In this paper we propose a design methodology based on high-level synthesis which takes into account multiple bit-width standards in order to generate area and power optimized architectures for embedded devices. First results demonstrate the interest of the approach.

1 :	Laboratoire de l'intégration, du matériau au système (IMS)

	CNRS : UMR5218 – Université Sciences et Technologies - Bordeaux I – Institut Polytechnique de Bordeaux

2 :	R2D2 (INRIA - IRISA)

	CNRS : UMR6074 – INRIA – Institut National des Sciences Appliquées (INSA) - Rennes – Ecole Nationale Supérieure des Sciences Appliquées et de Technologie (ENSSAT) – Université de Rennes 1

Domaine

Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique


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Contributeur : Bertrand Le Gal <>
Soumis le : Mercredi 17 Octobre 2007, 11:03:10
Dernière modification le : Mercredi 17 Octobre 2007, 11:03:10