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fulltext access A clock network of distributed ADPLLs using an asymmetric comparison strategy
Korniienko A., Colinet E., Scorletti G., Blanco E., Galayko D., Juillard J.
In Proceedings of the IEEE International Symposium on Circuit and Systems (ISCAS'10) - IEEE International Symposium on Circuit and Systems (ISCAS'10), France (2010) [hal-00520988 - version 1]