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| HAL : inria-00481135, version 1 |
| Voir la fiche détaillée |  BibTeX,EndNote,... |
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| Worshop on Combinatorial Optimization for Embedded System Design (COESD 2010), Bologne : Italy (2010) |
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| Graph Constraints in Embedded System Design |
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| Christophe Wolinski 1Krzysztof Kuchcinski 2 |
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| (15/06/2010) |
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| In this paper, we present application of graph constraints combined with finite domain constraints for embedded system optimization problems. In particular, we present methods for identification and selection of computational patterns as well as application scheduling with these patterns that has direct application in ASIP processor design. In this work we use connected component, (sub)graph isomorphism and clique constraints. Our experimental results show that these methods work for relatively large examples and provide much better results than previous heuristic based approaches. |
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| 1 : | CAIRN (INRIA - IRISA) |
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INRIA – CNRS : UMR6074 – École normale supérieure de Cachan - ENS Cachan – Institut National des Sciences Appliquées (INSA) - Rennes – Université de Rennes 1 |
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| 2 : | Department of Computer Science [Lund] |
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Lund University |
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| Domaine | : | Informatique/Architecture |
| inria-00481135, version 1 | |
| http://hal.inria.fr/inria-00481135 | |
| oai:hal.inria.fr:inria-00481135 | |
| Contributeur : François Charot | |
| Soumis le : Jeudi 6 Mai 2010, 09:21:35 | |
| Dernière modification le : Vendredi 7 Mai 2010, 09:37:10 | |
