3256 articles – 5421 references  [version française]
HAL: hal-00294132, version 1

Detailed view  Export this paper
3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008., Tozeur : Tunisie (2008)
New Directions in Interconnect Performance Optimization
Antoine Courtay 1, 2, Johann Laurent 2, Nathalie Julien 2, Olivier Sentieys 1
(2008-03-25)

It is now admitted that interconnects represent a bottleneck for delay, power consumption and area on chips. To face these problems some works have been realized around performance optimizations. However results, presented in this paper, show that optimization techniques do not always face good criteria for interconnect performance optimizations. We therefore have developed a high-level estimation tool based on transistor-level characterizations, which provides users fast and precise results for time and power consumption estimation. Estimation results allowed us to determine a new interconnect consumption model and also enabled to find some new key issues that have to be pointed out for future performance optimizations.
1:  CAIRN (INRIA - IRISA)
INRIA – CNRS : UMR6074 – École normale supérieure de Cachan - ENS Cachan – Institut National des Sciences Appliquées (INSA) - Rennes – Université de Rennes 1
2:  Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC)
CNRS : UMR3192 – Université de Bretagne Occidentale [UBO] – Université de Bretagne Sud – Institut Mines-Télécom – Télécom Bretagne – PRES Université Européenne de Bretagne [UEB] – Institut Supérieur des Sciences et Technologies de Brest (ISSTB)
Lab-STICC_UBS_CACS_MOCS
Lab-STICC_UBS_CACS_CS,Lab-STICC_UBS_CACS_MOCS
Engineering Sciences/Micro and nanotechnologies/Microelectronics
Interconnect – Power Consumption – Timing – Modelling – Estimation – Performance optimization