Critical sensitivity of flash gate dimension spread on electrical performances for advanced embedded memory

El Amine Agharben (1) , A. Roussy (2) , Marc Bocquet (3) , M. Bileci (1) , S Bégouin (1) , A. Marchadier (1)

1 ST-ROUSSET - STMicroelectronics [Rousset]
2 EMSE-CMP - Ecole Nationale Supérieure des Mines de Saint-Etienne, Centre Microélectronique de Provenc
3 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence

In this paper a correlation between specific inline and electrical parameters has been deeply investigated. This study shows the impact of the flash gate intra-die and intra-wafer spread on the memory performances. A process recipe optimization has been evaluated to recover the effects of these variations. This optimization allows us to reduce the written threshold voltage intra-wafer spread by fifty percent.

Mots clés: Non Volatile Memory; Embedded Memory; Semiconductor; Intra-wafer Variability; Intra-Die spread

Domaines: Micro et nanotechnologies/Microélectronique

El Amine Agharben, A. Roussy, Marc Bocquet, M. Bileci, S Bégouin, et al.. Critical sensitivity of flash gate dimension spread on electrical performances for advanced embedded memory. 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), May 2015, Saratoga Springs, United States. ⟨10.1109/ASMC.2015.7164428⟩. ⟨hal-01737953⟩