Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors
Résumé
In the last decade, many papers have been published to present sequential connected component labeling (CCL) algorithms. As modern processors are multi-core and tend to many cores, designing a CCL algorithm should address parallelism and multithreading. After a review of sequential CCL algorithms and a study of their variations, this paper presents the parallel version of the Light Speed Labeling for Connected Component Analysis (CCA) and compares it to our parallelized implementations of State-of-the-Art sequential algorithms. We provide some benchmarks that help to figure out the intrinsic differences between these parallel algorithms. We show that thanks to its run-based processing, the LSL is intrinsically more efficient and faster than all pixel-based algorithms. We show also, that all the pixel-based are memory-bound on multi-socket machines and so are inefficient and do not scale, whereas LSL, thanks to its RLE compression can scale on such high-end machines. On a 4×15-core machine, and for 8192×8192 images, LSL outperforms its best competitor by a factor ×10.8 and achieves a throughput of 42.4 gigapixel labeled per second.
Domaines
Algorithme et structure de données [cs.DS] Architectures Matérielles [cs.AR] Traitement du signal et de l'image [eess.SP] Vision par ordinateur et reconnaissance de formes [cs.CV] Automatique / Robotique Traitement du signal et de l'image [eess.SP] Arithmétique des ordinateurs Calcul parallèle, distribué et partagé [cs.DC] Génie logiciel [cs.SE] Mathématique discrète [cs.DM] Robotique [cs.RO] Traitement des images [eess.IV]
Origine : Fichiers produits par l'(les) auteur(s)
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