The eISP low-power and tiny silicon footprint programmable video architecture

Thevenin Mathieu (1) , Michel Paindavoine (2) , Letellier Laurent (3) , Schmit Renaud (3) , Barthélémy Heyrman (4)

1 LCEI - Laboratoire Calculateurs Embarqués et Image
2 LEAD - Laboratoire d'Etude de l'Apprentissage et du Développement [Dijon]
3 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies
4 Le2i - Laboratoire Electronique, Informatique et Image [UMR6306]

CMOS sensors are now more and more frequently integrated into popular consumer products. Images from these sensors thus need to be digitally processed for display purposes. To do so, CMOS sensors are associated with dedicated components that keep power consumption low. However, use of dedicated components limits hardware flexibility and prevents updating of image processing algorithms. This paper describes the eISP, a programmable processing architecture that combines enough computational efficiency for 1080p HD video with silicon area and power characteristics suitable for the next generation of mobile phones (lower than 1 mm2 and 500 mW in TSMC 65 nm).

Mots clés: Embedded programmable image video processor; Low power; CMOS; High definition; VLIW; Video pipe

Domaines: Electronique

Thevenin Mathieu, Michel Paindavoine, Letellier Laurent, Schmit Renaud, Barthélémy Heyrman. The eISP low-power and tiny silicon footprint programmable video architecture. Journal of Real-Time Image Processing, 2011, 6 (1), pp.33-46. ⟨10.1007/s11554-010-0163-8⟩. ⟨hal-01104558⟩